1. Field of the Invention
The present invention relates generally to an integrated circuit (IC) which comprises an analog switch(es) and digital circuitry, both sharing external input and/or output terminals and being coupled to different power sources. More specifically, the present invention relates to such an IC wherein a back gate voltage controller is provided for preventing a leak current flowing through the analog switch while the switch is not in use.
2. Description of the Related Art
It is known in the art to provide, on the identical IC chip, an analog switch(es) and digital circuitry, which are respectively coupled to different power sources.
Before turning to the present invention, it is deemed advantageous to briefly describe, with reference to FIGS. 1 to 3, a known circuit relevant to the present invention.
Referring to FIG. 1, there are schematically shown an analog multiplexer 10 and a digital circuit 12 both provided on the same chip. As shown, the analog multiplexer 10 comprises a p-channel analog switch 14, a CMOS (complementary metal oxide semiconductor) analog switch 16, and an n-channel analog switch 18. Although not shown in FIG. 1, one or more other n-channel analog switches may be coupled between the switches 16 and 18. The p-channel analog switch 14 has the source and drain, which are respectively coupled to a voltage divider 20 and an output terminal 22. This output terminal 22 is coupled to external circuitry (not shown) and is shared by the digital circuit 12. The on/off operation of the analog switch 14 is implemented by a digital control signal applied to the gate thereof, via a digital inverter 24, from a gate control terminal 26. The back gate of the analog switch 14 is directly coupled to the power source VDD (1).
The CMOS analog switch 16 is constructed using two paralleled complementary MOSFETs (field-effect transistors) 16a and 16b. The source of the MOSFET 16a is directly coupled to the drain of the MOSFET 16b and the voltage divider 20. On the other hand, the drain of the MOSFET 16a is directly coupled to the source of the MOSFET 16b, and these terminals are coupled to the output terminal 22. The on/off operation of the CMOS analog switch is controlled by a digital control signal applied to the gates of the MOSFETs 16a and 16b from a gate control terminal 28. It is to be noted that each of digital inverters 24 and 25 is provided to reverse the polarity of the gate control signal. The back gates of the MOSFETs 16a and 16b are respectively coupled to the power source VDD(1) and ground VSS.
As in the above-mentioned analog switch 14, the n-channel analog switch 18 has the drain and source, which are respectively coupled to the voltage divider 20 and the output terminal 22. The on/off operation of the analog switch 18 is carried out by a digital control signal applied to the gate thereof from a gate control terminal 30. The back gate of the analog switch 18 is directly coupled to ground VSS.
When the analog multiplexer 10 is used, the digital circuit 12 is not used, and vice versa.
As shown, the digital circuit 12 comprises two complementary MOSFET switches 12a and 12b which are provided in series between a power source VDD(2) and ground VSS. When the MOSFETs 12a and 12b are respectively turned on and off by applying gate control signals from terminals 32 and 34, the voltage of the power source VDD(2) appears at the output terminal 22. Contrarily, when the MOSFETs 12a and 12b are respectively turned off and on, the output terminal 22 is pulled to ground.
FIG. 2 is a diagram showing the p-channel analog switch 14 of FIG. 1, and FIG. 3 is a cross-sectional schematic of the structure of the switch 14. The configuration of the p-channel analog switch per se is well known in the art and thus only a brief description thereof is given.
As shown in FIG. 3, a p-channel is formed between the source and the drain which are respectively p+ diffusion regions 40 and 42 formed in an n-well. The back gate (denoted by 44) is separated from the active region by forming an isolator 46 and is directly coupled to the power source VDD(1). Assume that the power source VDD(1) is lowered for some reasons such as reducing power dissipation (for example) when the analog multiplexer 10 is not used. In this case, if the digital circuit 12 outputs the power source voltage (vix., VDD(2)), a current undesirably flows from the drain 42 and the source 40 to the back gate 44 because the p-n junction therebetween is forward biased. Therefore, according to the related are in question, the power source VDD(1) should not be lowered (vix., kept to be applied to the back gate 44) even if the analog multiplexer 10 is not in use.
Japanese Laid-open Patent Application No. 5-276001 discloses an analog switch circuit wherein an n-channel transistor has a substrate that is selectively coupled to ground via an n-channel transistor. However, this related art fails to disclose a combination of an analog switch and digital circuitry, both sharing external input and/or output terminals and being coupled to different power sources.
However, it is highly desirable that when the analog switch is not utilized while the digital circuitry is utilized, the analog input voltage can be lowered for the purpose of power conservation.
It is therefore an object of the present invention to provide a back gate voltage controller for preventing a leak current when an analog switch is not in use even if an analog power source is lowered.
One aspect of the present invention resides in a semiconductor device comprising an analog switch and digital circuitry, both being formed on a single integrated circuit chip and sharing a node coupled to external circuitry, comprising: a first power source coupled to an input terminal of the analog switch whose output is operatively coupled to the node; a second power source for supplying electric power to the digital circuitry whose input or output is operatively coupled to the node; and a back gate voltage controller, coupled to a back gate of the analog switch, for controlling a voltage applied to the back gate in response to an operation mode control signal for determining whether the analog switch or the digital circuitry is to be enabled.